1. Field of the Invention
The present invention relates to an information processing apparatus such as personal computers and work stations, and in particular to protocols of buses of these information processing apparatuses and internal buses of LSIs used in the information processing apparatus.
2. Description of the Related Art
As for the conventional technique concerning buses used in information processors such as personal computers and work stations, and concerning control methods of the buses, there is known a technique described in U.S. Pat. No. 5,428,753 assigned to the present assignee. As described therein, a synchronous bus has become a main stream since the design of the interface circuit is facilitated. In the synchronous bus, a plurality of modules connected to the bus conduct data transmission and reception control in synchronism with common clock timing. A typical synchronous bus configuration and its timing chart are shown in FIGS. 13 and 14, respectively. In FIG. 13, numeral 1300 denotes a clock generator for distributing a common system clock among modules, Numerals 1301, 1302 and 1303 denote modules on a bus. Numeral 1301 denotes a master module serving as a transfer source of data. Numeral 1303 denotes a slave module serving as a transfer destination of data, and numeral 1304 denotes a data bus. With reference to FIGS. 13 and 14, numerals 1400 and 1401 denote timing relations between a system clock and output data observed on an output pin of the master module 1301 serving as the transfer source of data. Numerals 1402 and 1403 denote timing relations between the system clock and input data observed on an input pin of the slave module 1303 serving as the transfer destination of data. The clocks 1400 and 1402 are distributed from the clock generator 1300 of FIG. 13 with the same phase. Data on the input pin of the slave module 1303 is delayed from that on the output pin of the master module 1301 by a propagation delay time on the data bus 1304. Since data must be transferred from the master module to the slave module in one cycle, the maximum operation frequency is typically determined on a synchronous bus by a maximum propagation delay time of the bus.
For solving this problem and further raising the frequency, a bus of a xe2x80x9csource clock synchronous systemxe2x80x9d (or a source clock synchronous bus) is conceivable. In the xe2x80x9csource clock synchronous systemxe2x80x9d, a module serving as a transfer source transmits a latch clock to be used in a module of a transfer destination together with transfer data. A bus configuration and a timing chart of a typical source clock synchronous system are shown in FIGS. 15 and 16, respectively. In FIG. 15., numeral 1500 denotes a signal line for a source clock which is transmitted from a master module serving as a transfer source to a slave module serving as a transfer destination. With reference to FIG. 16, numerals 1600 and 1601 denote timing relations between a source clock and output data observed on an output pin of the master module serving as the transfer source of data. Numerals 1602 and 1603 denote timing relations between the source clock and input data observed on an input pin of the slave module serving as the transfer destination of data. If a source clock line and a data line are mounted on similar wiring paths in the bus of the source clock synchronous system, the source clock and the data are delayed by the same phase, and consequently failures of data acquisition are reduced. In other words, the maximum operation frequency of the bus is not reflected at the time of data propagation delay. (Because data are further delayed in a remote module, but the latch clock is also delayed by the same phase.) Typically, the bus of the source clock synchronous system is such a bus that the operation frequency can be raised easily.
However, the synchronous bus is more excellent in easiness of design. A control method of signals of an acknowledge type for each transfer cycle as described in, for example, U.S. Pat. No. 5,428,753 will now be considered. FIG. 17 shows transfer timing of the synchronous bus with a protocol of the acknowledge type. In FIG. 17, numeral 1700 denotes a system clock common to modules on the bus, numeral 1701 denotes transfer data timing, and numeral 1702 denotes acknowledge signal timing. If it is determined in the synchronous bus that a signal of the acknowledge type is issued necessarily two cycles after the data transfer cycle, association of transfer data with the report of the acknowledge type is very easy. As for the protocol of the acknowledge type, there are, for example, an acknowledge for notifying the master side that the slave side has certainly received data, a retry request for requesting the master side to retransfer data later because the slave side is not ready to receive data, and an error report for notifying the master side that data received by the slave side contained an error (such as a parity error). In the bus of the source clock synchronous system allowing data transfer at a clock frequency unique to an individual module, there is a possibility that the master side and the slave do not have the same clock system. Therefore, there is a problem that it is difficult to add a protocol of the acknowledge and the retry request. An
An object of the present invention is to provide a bus of source clock synchronous system with a protocol of an acknowledge type in order to operate the bus with high reliability and a high efficiency and provide an information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system.
In the present invention, there is provided a source clock signal dedicated to acknowledge type signals on a signal line of a bus in order to transfer the acknowledge type signals as well by using the source clock synchronous system. Furthermore, in order to make possible control even if there are mixedly modules having different operation frequencies, an acknowledge signal is not provided for each cycle, but is provided for each basic transfer block having a substantial number of cycles.
Since the acknowledge type signals are also transferred in the source clock synchronous system by using a source clock signal dedicated to the acknowledge type signals, a failure, on the master side, of acquisition of an acknowledge type signal from the slave side is prevented. Furthermore, since an acknowledge signal is provided for each basic transfer block having a substantial number of cycles, control becomes possible even if there are mixedly modules having different operation frequencies.
In other words, in accordance with the present invention, there are provided a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the bus, there is provided a source clock signal line dedicated to the acknowledge type signals. As the master module, a processor or an I/O (input/output) device is conceivable. As the slave module, an I/O device or a storage is conceivable.
As for signals based upon the protocol of the acknowledge type, there are an acknowledge report indicating that the transfer from the master module to the slave module has been conducted, a retry request for requesting reexecution because the slave module is not ready to receive data transferred from the master module, and an error report for notifying the master module that transfer from the master module to the slave module has not been conducted correctly.
Furthermore, the acknowledge report and the retry request are sent once for a plurality of transfer cycles.
Furthermore, a method for transferring a signal of an acknowledge type includes the steps of transferring data and a source clock used as a latch clock from a master module to a slave module serving as a transfer destination via a bus of a source clock synchronous system, and transferring a signal based upon a protocol of the acknowledge type together with a source clock of the slave module from the slave module to the master module via the bus when the slave module has received the data and the latch clock transferred from the master module.